PCI Express 3.0 Details Announced

PCI-SIG, the Special Interest Group responsible for PCI Express industry-standard I/O technology, announced the approval of next generation of PCIe architecture, PCIe 3.0

Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, PCI-SIG's analysis found out that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCIe protocol stack.

PCIe 2.0 delivers 5GT/s but employed an 8b/10b encoding scheme which took 20 percent overhead on the overall raw bit rate. By removing the requirement for the 8b/10b encoding schem, PCIe 3.0's 8GT/s bit rate -effectively- delivers double PCIe 2.0 bandwidth. The PCIe 3.0 specification will also introduce a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies. The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond.

"Experts in the PCIe Electrical Workgroup analyzed both 10GT/s and 8GT/s as target bit rates for the next generation of PCIe architecture, and after careful consideration of several factors, including power, implementation complexity and silicon area, recommended 8GT/s", said Al Yanes, PCI-SIG chairman. "This allows us to satisfy the next generation performance requirements for all existing PCIe applications while maintaining backward compatibility, and at the same time broadening the adoption of this pervasive technology into new and emerging applications and usage models."

PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG.

The transition from PCIe 1 to PCIe 2 is still to take place in Q3 2007 with Intel's X38 chipset. AMD will support PCIe 2.0 starting from its RD700 chipset series. NVIDIA has revealed that the MCP72 will be their first PCIe 2.0 equipped chipset.

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