In IBM's labs, miniscule rivers of water are cooling computer chips that have circuits and components stacked on top of each other, a design that promises to extend Moore's Law into the next decade and significantly reduce the energy consumed by data centers.
IBM scientists unveiled a powerful and efficient technique to cool 3-D chip stacks with water. In collaboration with the Fraunhofer Institute in Berlin, they demonstrated a prototype that integrates the cooling system into a 3-D chip by piping water directly between each layer in the stack.
These so-called 3-D chip stacks-in which chips and memory devices that traditionally sit side-by-side on a silicon wafer are layered on top of one another-presents one of the most promising approaches to enhancing chip performance beyond its predicted limits.
A year ago IBM revealed that, by stacking transistors in a 3-D chip, they managed to drastically shorten the distance that information needs to travel on a chip to just 1/1000th of that on 2-D chips while allowing the addition of up to 100 times more channels, or pathways, for that information to flow.
IBM researchers are exploring concepts for stacking memory on top of processors and, ultimately, for stacking many layers of processor cores. But in such advanced scenarios, cooling becomes a formidable challenge.
"As we package chips on top of each other to significantly speed a processor's capability to process data, we have found that conventional coolers attached to the back of a chip don't scale. In order to exploit the potential of high-performance 3-D chip stacking, we need interlayer cooling," explains Thomas Brunschwiler, project leader at IBM's Zurich Research Laboratory: "Until now, nobody has demonstrated viable solutions to this problem."
Such 3-D chip stacks would have an unprecedented aggregated heat dissipation of close to 1 kilowatt in a volume of just half a cubic centimeter -10 times higher than any other human-made device. Most notably, power densities in these stacked processors are higher than in nuclear and plasma reactors.
Brunschwiler and his team piped water into cooling structures as thin as a human hair (50 microns) between the individual chip layers in order to remove heat efficiently at the source. Using the superior thermophysical qualities of water, scientists were able to demonstrate a cooling performance of up to 180 W/cm2 per layer for a stack with a typical footprint of 4 cm2. "This truly constitutes a breakthrough. With classic backside cooling, the stacking of two or more high-power density logic layers would be impossible," states Bruno Michel, manager of the chip cooling research efforts at the IBM Zurich Lab.
In their experiments, IBM scientists piped water through a 1 by 1 cm test vehicle, consisting of a cooling layer between two dies or heat sources. The cooling layer measures only about 100 microns in height and is packed with 10,000 vertical interconnects per cm2. The team overcame key technical challenges in designing a system that maximizes the water flow through the layers, yet hermetically seals the interconnects to prevent water from causing electrical shorts. The complexity of such a system resembles that of a human brain, wherein millions of nerves and neurons for signal transmissions are intermixed but do not interfere with tens of thousands of blood vessels for cooling and energy supply, all within the same volume.
The fabrication of the individual layers was accomplished with existing 3-D packaging fabrication methods to etch or drill the holes for signal transmission from one layer to the next. To insulate these "nerves", scientists left a silicon wall around each interconnect (also called through silicon vias) and added a fine layer of silicon oxide to insulate the electrical interconnects from the water. The structures had to be fabricated to an accuracy of 10 microns, 10 times more accurate than for interconnects and metallizations in current chips.
To assemble the individual layers, Brunschwiler with colleagues from the Fraunhofer Institute developed a sophisticated thin-film soldering technique. Using this technique, scientists achieved the high quality, precision and robustness needed to ensure excellent thermal contacts as well as electrical contacts without shorts. In the final setup, the assembled stack is placed in a silicon cooling container resembling a miniature basin. The water is pumped into the container from one side and flows between the individual chip layers before exiting at the other side.
Using simulations, scientists extrapolated the experimental results of their test vehicle to a 4-cm2 chip stack and achieved a cooling performance of 180 W/cm2.